1. Field of the Invention
The present invention relates to a semiconductor device which achieves reduction in size of a formation region of an isolation region and in size of the device while maintaining breakdown voltage characteristics, and also relates to a manufacturing method thereof.
2. Description of the Related Art
As an embodiment of a conventional semiconductor device, a structure of the following NPN transistor 141 has been known. As shown in FIG. 15, an N type epitaxial layer 143 is formed on a P type semiconductor substrate 142. In the epitaxial layer 143, P type buried diffusion layers 144 and 145, which are diffused in a vertical direction (a depth direction) from a surface of the substrate 142, and P type diffusion layers 146 and 147, which are diffused from a surface of the epitaxial layer 143, are formed. Moreover, the epitaxial layer 143 is divided into a plurality of element formation regions by isolation regions 148 and 149 which are formed by connecting the P type buried diffusion layers 144 and 145 with the P type diffusion layers 146 and 147, respectively. In one of the element formation regions, for example, the NPN transistor 141 is formed. The NPN transistor 141 is mainly formed of an N type buried diffusion layer 150 used as a collector region, a P type diffusion layer 151 used as a base region and an N type diffusion layer 152 used as an emitter region. Moreover, the P type buried diffusion layers 144 and 145, which respectively form the isolation regions 148 and 149, are diffused by placing the substrate 142, for example, in a nitrogen atmosphere at 1050° C. for approximately 1 hour and subjecting the substrate to a dedicated heat treatment. Meanwhile, the P type diffusion layers 146 and 147, which respectively form the isolation regions 148 and 149, are diffused by placing the substrate 142, for example, in a nitrogen atmosphere at 1000° C. for approximately 2 hours and subjecting the substrate to a dedicated heat treatment. By these thermal diffusion steps, the P type buried diffusion layer 144 and the P type diffusion layer 146 are connected with each other to form the isolation region 148, and the P type buried diffusion layer 145 and the P type diffusion layer 147 are connected with each other to form the isolation region 149. This technique is described for instance in Japanese Patent Application Publication No. Hei 9 (1997)-283646 (Pages 3, 4 and 6, FIGS. 1 and 5 to 7).
As described above, in the conventional semiconductor device, the thickness of the epitaxial layer 143 is determined by taking account of the breakdown voltage of the NPN transistor 141 and the like. For example, in the case where a power semiconductor element and a control semiconductor element are monolithically formed on the same semiconductor substrate 142, the thickness of the epitaxial layer 143 is determined according to breakdown voltage characteristics of the power semiconductor element. Moreover, the P type buried diffusion layers 144 and 145, which respectively form the isolation regions 148 and 149, expand upward from the surface of the substrate 142 into the epitaxial layer 143. Meanwhile, the P type diffusion layers 146 and 147, which respectively form the isolation regions 148 and 149, expand downward from the surface of the epitaxial layer 143. This structure allows lateral diffusion widths W15 and W16 of the P type buried diffusion layers 144 and 145 to be increased with the increase of the upward expansion widths thereof. Accordingly, this structure has a problem that it is difficult to reduce in size of formation regions of the isolation regions 148 and 149.
Moreover, in the conventional semiconductor device, the epitaxial layer 143 is formed on the semiconductor substrate 142. The NPN transistor 141 is formed in a region defined by the isolation regions 148 and 149 in the epitaxial layer. Moreover, the epitaxial layer 143 is a region with a low concentration of the N type impurity. This structure allows a formation region of the P type buried diffusion layer 144 or a P type diffusion layer 151 to be shifted, and thereby allows a distance L5 between the both diffusion layers 144 and 151 to be shorten. Thus, a region in which a depletion layer expands is reduced in size. Accordingly, in the NPN transistor 141, short-circuiting is likely to occur between the base region and the isolation region. Thus, there is a problem that it is difficult to obtain desired breakdown voltage characteristics. Moreover, there is a problem that a variation in the distance L5 makes unstable the breakdown voltage characteristics of the NPN transistor 141.
Moreover, in the conventional semiconductor device, in order to achieve a desired breakdown voltage of the NPN transistor 141, it is required that the distance L5 between the P type diffusion layer 151 and the P type buried diffusion layer 144 in the isolation region 148 be a certain distance or more. Similarly, a distance L6 between the P type diffusion layer 151 and the P type diffusion layer 146 in the isolation region 148 is required to be a certain distance or more. However, there is a problem that the increase in the lateral diffusion widths W15 and W17 of the P type buried diffusion layer 144 and the P type diffusion layer 146, which form the isolation region 148, makes it difficult to reduce a device size of the NPN transistor 141.
Moreover, in a conventional method for manufacturing the semiconductor device, the two thermal diffusion steps described above are performed to connect the P type buried diffusion layers 144 and 145 with the P type diffusion layers 146 and 147 to form the isolation regions 148 and 149, respectively. This manufacturing method allows lateral diffusion widths W15 and W16 of the P type buried diffusion layers 144 and 145 to be increased with the increase of the corresponding upward expansion widths thereof. Moreover, by the thermal diffusion steps, the N type buried diffusion layer 150 also expands toward the surface of the epitaxial layer 143. As a result, a problem arises that it is difficult to reduce the thickness of the epitaxial layer 143, to reduce in size the formation regions of the isolation regions 148 and 149, and also to reduce the device size of the NPN transistor 141.
Furthermore, description will be given of a structure in which, as shown in FIG. 16, NPN transistors 161 and 162 are adjacent to each other with an isolation region 163 interposed therebetween. A ground voltage (GND) is applied to a collector region of the NPN transistor 161, and a power supply voltage (Vcc) is applied to a collector region of the NPN transistor 162. In this case, in the NPN transistor 162, a reverse bias is applied to a PN junction region of the P type isolation region 163 and a P type semiconductor substrate 164 with an N type epitaxial layer 165 and an N type buried diffusion layer 166. Moreover, depletion layers spread from the PN junction regions toward the P type isolation region 163 and the P type semiconductor substrate 164.
In this event, when an impurity concentration in an overlapping region between a P type buried diffusion layer 167 and a P type diffusion layer 168 is lowered in the isolation region 163, a depletion layer spreads into the NPN transistor 161 as indicated by a dotted line. Moreover, when spreading of the depletion layer reaches an N type buried diffusion layer 169, a problem arises that the collector regions of the NPN transistors 161 and 162 are short-circuited to cause a leak current. Meanwhile, in order to prevent the leak current, it is required to more widely diffuse the P type buried diffusion layer 167 and the P type diffusion layer 168, and thereby to increase the impurity concentration in the overlapping region. However, in this case, a diffusion width W18 of the P type buried diffusion layer 167 and a diffusion width W19 of the P type diffusion layer 168 are increased. Thus, there is a problem that it is difficult to reduce a device size of each of the NPN transistors 161 and 162.